Sr Staff Verification Engineer ( 数字验证工程师)

Job Description

+ Understanding the expected functionality of designs.
+ Designing and developing verification environment
+ Improve the verification architecture and flow
+ Running RTL and gate-level simulations/regression.
+ Code/functional coverage development, analysis and closure.

Qualifications

+ Bachelor degree or master degree in CS/ME.
+ Minimum of 8 years’ experience.
+ Candidate should be familiar with as System Verilog, UVM verification.
+ Have Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
+ Independent and self-managing.
+ Familiar with UVM source code or key UVM mechanism
+ Familiar with industry standard verification tools and flow.
+ Familiar with basic computer architecture

Additional qualifications include:

+ Good IC verification skills and basic knowledge of logic and circuit design, goo...