THE ROLE:

This leader plays a key role in SoC DV flow, he/she will mainly focus on chip level DFX functions verification tasks and drive the DV team’s execution with high quality in a good schedule manner. Moreover, he/she is expected to support post-silicon ATE test to achieve the desired silicon bring up target.

THE PERSON:

Good team worker with solid Verilog RTL design and verification knowledge/experience. Knowledge reservation on System_Verilog/UVM/Modeling/Scan/BIST will be a strong plus.

KEY RESPONSIBILITIES:

• Cutting-edge test strategies study and implementation.
• Allocate DFX DV Resource and organize periodic DFX DV quality review.
• Responsible for key design milestone DFX DV checklist signoff.
• SoC DFX test plan development based on design specification and DFX feature list.
• Responsible for SoC DFX testbench development and maintenance.
• Responsible for SoC level DFX test ca...