Our client is looking for a Principal Engineer – High-Speed SerDes System Architect to lead next-gen high-speed wireline electrical communication research . Join their High-Speed High-Frequency team within the Board Engineering Lab at their Grenoble Research Center , collaborating closely with HQ technical teams in China to develop 112 Gbit/s+ SerDes systems .

Location: Grenoble Research Center (On-site)
Salary: €90,000 - €150,000 per annum
Employment Type: Permanent

Key Responsibilities

• High-Speed Research & Innovation – Lead research in high-speed wireline electrical communications, developing new system architectures, designs, models & simulations
• Next-Gen SerDes Development – Explore SerDes PHY architectures (signaling, equalization, FEC) for hyperscale data centers & AI infrastructure
• Algorithm Dev...