Owns the process development and technical support of the Flip Chip process for silicon photonic chip wafers, with OSAT or internal line. Process may include plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.
DOE to characterize process window and margin. Optimize process integration with upstream processes (e.g. bump/FO) to increase yield and manufacturability.
Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including NCP, flux, underfill etc, as applicable.
Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).
Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to FC (e.g. flux void, residue, misalign...
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