SkyeChip in Malaysia is seeking a Physical Design Lead to own and drive the end-to-end implementation of testchips and high-speed interface subsystems including DDR/LPDDR PHY and HBM PHY. This role will require mentoring junior engineers and collaborating across teams.

The ideal candidate will have 7–10+ years of experience and multiple tape-outs at sub-10nm process nodes.

Expertise in P&R tools such as Cadence Innovus and the ability to enforce design methodologies are essential.