Work closely with front end design engineers to translate RTL-to-GDSII. Responsible for all aspects of physical design and implementation. Participate in the efforts of establishing physical design methodologies and flow automation. Work on chip and block floorplan, power/ clock distribution, chip assembly, P&R, and timing closure. Implement and monitor Quality Assurance/Quality Control standards based on corporate guidelines in a project setting. Train/mentor new employees.

JOB DESCRIPTION/OTHER RECRUIREMENT:

• Power planning, optimization, power grid and signal routing considering timing constraints.
• Design floor planning, analogue and memory macro placement.
• Place and route including timing closure.
• Extraction of layout parasitics and SPEF/ SDF generation. Signal integrity tests.
• Post-synthesis static timing analysis (STA) and post-layout STA.
• Physica...