We are looking for a motivated Physical Design Engineer to join our Renesas team who can work independently with little or no supervision.  Our candidate should be able to execute physical design flow (RTL-GDSII & STA) per planned schedule, assess risk and meet all deliverables. Candidate must monitor and drive the program from initiation to tapeout, interfacing with internal and external stakeholders and achieve alignment across cross-functional teams.

Responsibilities:

• Drive block level/full chip Place & route and timing closure (Synthesis, PNR, STA and Physical verification).
• Closely work with mixed signal custom design team on full chip floorplan to integrate analog macros
• Perform Physical verification DRC, LVS, Antenna & IR-EM checks and fixing errors
• Run timing analysis, debug timing violations and implement functional, timing ECOs and perform formal verification.
• Work o...