Key Responsibilities:

• Interface with ASIC design teams to ensure DFT design rules and coverages are met.
• Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.
• MBIST verification (including repair), test pattern generation through Mentor tool.
• ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
• Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
• Responsible for supporting post-silicon debug effort, issue resolution.
• Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.
• Developing, enhancing and maintaining scripts as necessary.

Preferred Experience:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering
• 7 to 15 years' experience in ASIC/D...