Position Overview

We are seeking an experienced DFT Engineer with strong expertise in Design-for-Test methodologies for complex ASIC/SoC designs. The ideal candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage, manufacturability, and silicon quality for next-generation semiconductor products.

The role requires deep understanding of scan insertion, ATPG, MBIST, JTAG, compression techniques, and SoC-level DFT integration flows.

Key Responsibilities