Job Details

Job Type: Experienced Hire

Shift: Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Work Model: Hybrid – employees may work on-site at the assigned Intel site and off-site.

Responsibilities

Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions. Perform functional simulation and verification to ensure designs meet functional and performance specifications. Debug and resolve design and simulation issues, collaborating closely with architects, verification engineers, and system teams to clarify requirements, and support design integration, bring‑up, and issue resolution. Ensure high design quality by following coding standards and maintaining proper technical documentation.

Minimum Qualifications

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog.
• Demonstrable experience in logic design and writing RTL in Verilog or...